Merge branch 'master' of https://gitlab.com/py_ren/pyren into master
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commit
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86
pyren/macro/init.txt
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86
pyren/macro/init.txt
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@ -0,0 +1,86 @@
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#
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#
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# Initialisation macros for mod_term
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#
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#
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$addr = 7A
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$txa = 7E0
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$rxa = 7E8
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# reset elm
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reset_elm {
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at ws
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$prompt = ELM
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}
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# general CAN init
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init_can {
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reset_elm #macro
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at e1
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at s0
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at h0
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at l0
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at al
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at caf0
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at cfc0
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at sh $txa
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at cra $rxa
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at fc sh $txa
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at fc sd 30 00 00
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at fc sm 1
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$prompt = CAN
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}
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# CAN 250 init
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can250 {
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init_can
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at st ff
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at at 0
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at sp 8
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at at 1
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$prompt = CAN250
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}
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# CAN 500 init
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can500 {
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init_can
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at st ff
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at at 0
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at sp 6
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at at 1
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$prompt = CAN500
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}
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# general ISO init
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init_iso {
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reset_elm #macro
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at e1
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at l1
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at d1
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at sh 81 $addr f1
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at sw 96
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at wm 81 $addr f1 3E
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#at wm 82 $addr f1 3E01
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at ib10
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at st ff
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at at 0
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$prompt = KL
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}
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# K-Line slow init
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slow {
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init_iso
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at sp 4
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at at 1
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$prompt = SLOW
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}
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# K-Line fast init
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fast {
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init_iso
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at sp 5
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at at 1
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$prompt = FAST
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}
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@ -465,7 +465,7 @@ class Port:
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continue
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self.buff += byte
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tc = time.time ()
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if 'ELM' or 'STN' in self.buff:
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if ('ELM' in self.buff) or ('STN' in self.buff):
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break
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if (tc - tb) > 1:
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print "ERROR - rate not supported. Let's go back."
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@ -645,7 +645,7 @@ class ScanEcus:
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ttrrsp = rrsp.replace(' ','')
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if not all(c in string.hexdigits for c in ttrrsp): return False
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while base+6<=len(row) and (int(row[base+3])*3+2)<=len(rrsp):
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while base+6<=len(row):
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if row[base]!=req:
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req = row[base]
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rrsp = self.elm.cmd(req)[3:]
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@ -654,7 +654,10 @@ class ScanEcus:
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if not all(c in string.hexdigits for c in ttrrsp): return False
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if len( req )/2==3: rrsp = rrsp[3:]
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if int(row[base+3])*3+2 > len(rrsp):
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return False
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byte = int(rrsp[int(row[base+3])*3:int(row[base+3])*3+2],16)
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mask = int(row[base+4],16)
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val = int(row[base+5],16)
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@ -691,8 +694,8 @@ class ScanEcus:
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if row['stdType']=='UDS':
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rerr = self.elm.cmd('1902AF') #get errors UDS
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if len(row['stopDiagReq'])>0:
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self.elm.cmd(row['stopDiagReq']) #close session
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#if len(row['stopDiagReq'])>0:
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# self.elm.cmd(row['stopDiagReq']) #close session
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self.elm.cmd("at at 1") #enable adaptive timing
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